6 6 6 65 5 5 5$ $ $ $0 0 0 0 2&72%(5 #4<<< 2&72%(5 #4<<< 2&72%(5 #4<<< 2&72%(5 #4<<< copyright ?1999 alliance semiconductor. all rights reserved. $6 : & 497 $6 : & 497 $6 : & 497 $6 : & 497 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 56 56 56 56 8 9 #; .[ ;# &026 # 65$0 8 9 #; .[ ;# &026 # 65$0 8 9 #; .[ ;# &026 # 65$0 8 9 #; .[ ;# &026 # 65$0 ? )hdwxuhv ? AS7C164 (5v version) ? commercial temperatur ? organization: 8,192 words 8 bits ? center power and ground pins ? high speed - 12/15/20 ns address access time - 3/4/5 ns output enable access time ? low power consumption: active - 550 mw (AS7C164) / max @ 12 ns ? low power consumption: standby - 11 mw (AS7C164) / max cmos i/o ?2.0v data retention ? easy memory expansion with ce1 , ce2, oe inputs ? ttl-compatible, three-state i/o ? 28-pin jedec standard package - 300 mil pdip and soj ? esd protection 3 2000 volts ? latch-up current 3 200 ma /rjlf # eorfn # gldjudp a 5 a 0 128648 array (65,536) input buffer a1 a2 a3 a4 a10 a11 a12 a 6 a 7 a 8 a 9 i/o0 i/o7 v cc gnd oe ce1 we column decoder row decoder control circuit sense amp ce2 3lq # duudqjhphqw 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 vcc we ce2 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 nc a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd 28-pin dip, soj (300 ml) 16 15 AS7C164 6hohfwlrq # jxlgh # AS7C164-12 AS7C164-15 AS7C164-20 unit maximum address access time 12 15 20 ns maximum output enable access time 3 4 5 ns maximum operating current 110 100 90 ma maximum cmos standby current 2.0 2.0 2.0 ma
6 6 6 65 5 5 5$ $ $ $0 0 0 0 $6 : & 497 $6 : & 497 $6 : & 497 $6 : & 497 ? 57 57 57 57 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 )xqfwlrqdo # ghvfulswlrq the AS7C164 is a high performance cmos 65,536-bit static random access memory (sram) device organized as 8,192 words 8 bits. it is designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 12/15/20 ns with output enable access times (t oe ) of 3/4/5 ns are ideal for high performance applications. active high and low chip enables ( ce1 , ce2) permit easy memory expansion with multiple-bank memory systems. when ce1 is high or ce2 is low the device enters standby mode. the standard AS7C164 is guaranteed not to exceed 11.0 mw power consumption in standby mode, and typically requires only 250 w; it offers 2.0v data retention with maximum power of 120 w. a write cycle is accomplished by asserting write enable (we ) and both chip enables (ce1 , ce2). data on the input pins i/o0-i/o7 is written on the rising edge of we (write cycle 1) or the active-to-inactive edge of ce1 or ce2 (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and both chip enables (ce1 , ce2), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input address. when either chip enable or output enable is inactive, or wr i te enable is active, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compatible, and operation is from a single 5v supply. the AS7C164 is packaged in all high v olume industry standard packages. $evroxwh # pd[lpxp # udwlqjv note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 7uxwk # wdeoh key: x = dont care, l = low, h = high parameter device symbol min max unit vo l t ag e o n v cc relative to gnd AS7C164 v t1 C0.50 +7.0 v voltage on any pin relative to gnd v t2 C0.50 v cc + 0.50 v power dissipation p d C1.0w storage temperature (plastic) t stg C65 +150 o c ambient temperature with v cc applied t bias C55 +125 o c dc current into outputs (low) i out C20ma ce1 ce2 we oe data mode h x x x high z standby (i sb , i sb1 ) x l x x high z standby (i sb , i sb1 ) l h h h high z output disable (i cc ) lhhld out read (i cc ) lhlxd in write (i cc )
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? $6 : & 497 $6 : & 497 $6 : & 497 $6 : & 497 # # # # ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 58 58 58 58 6 6 6 65 5 5 5$ $ $ $0 0 0 0 5hfrpphqghg # rshudwlqj # frqglwlrqv # '& # rshudwlqj # fkdudfwhulvwlfv #+ ryhu # wkh # rshudwlqj # udqjh , 1 &dsdflwdqfh #+ i 4 0+] /# 7 d 58 r # & /# 9 && # # 120,1$/ , 2 parameter device symbol min typical max unit supply voltage AS7C164 v cc 4.5 5.0 5.5 v input voltage AS7C164 v ih 2.2 C v cc +1 v v il C0.5 * * v il min = C3.0v for pulse width less than t rc /2. C0.8v ambient operating temperature AS7C164 t a 0C 70 o c parameter symbol test conditions device -12 -15 -20 unit min max min max min max input leakage current | i li | v cc = max, v in = gnd to v cc C1C1C1a output leakage current | i lo | v cc = max, ce1 = v ih or ce2 = v il , v out = gnd to v cc C1C1C1a operating power supply current i cc v cc = max, ce1 = v il , ce2 = v ih , f = f max, i out = 0 ma AS7C164 C 110 C 100 C 90 ma standby power supply current i sb v cc = max, ce1 = v ih or ce2 = v il , f = f max AS7C164 C 30 C 25 C 25 ma i sb1 v cc = max, ce1 3 v cc C0.2v or ce2 0.2v, v in 0.2v or v in 3 v cc C0.2v, f = 0 AS7C164 C 2.0 C 2.0 C 2.0 ma output voltage v ol i ol = 8 ma, v cc = min C 0.4 C 0.4 C 0.4 v v oh i oh = C4 ma, v cc = min 2.4 C 2.4 C 2.4 C v parameter symbol signals test conditions max unit input capacitance c in a, ce1 , ce2, we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
6 6 6 65 5 5 5$ $ $ $0 0 0 0 $6 : & 497 $6 : & 497 $6 : & 497 $6 : & 497 ? 59 59 59 59 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 5hdg # f\foh #+ ryhu # wkh # rshudwlqj # udqjh , 3,9 .h\ # wr # vzlwfklqj # zdyhirupv 5hdg # zdyhirup #4#+ dgguhvv # frqwuroohg , 3, 6, 7, 9, 12 5hdg # zdyhirup #5#+ &( 4 # dqg # &( 5# frqwuroohg , 3, 6, 8, 9, 12 parameter symbol -12 -15 -20 unit notes min max min max min max read cycle time t rc 12 C 15 C 20 C ns address access time t aa C12C15C20 ns3 chip enable (ce1 ) access time t ace1 C12C15C20 ns3, 12 chip enable (ce2) access time t ace2 C12C15C20 ns3, 12 output enable (oe ) access time t oe C3C4C5 ns output hold from address change t oh 3C3C3C ns5 ce1 low to output in low z t clz1 3C3C3C ns4, 5, 12 ce2 high to output in low z t clz2 3C3C3C ns4, 5, 12 ce1 high to output in high z t chz1 C3C4C5 ns4, 5, 12 ce2 low to output in high z t chz2 C3C4C5 ns4, 5, 12 oe low to output in low z t olz 0C0C0C ns4, 5 oe high to output in high z t ohz C3C4C5 ns4, 5 power up time t pu 0C0C0C ns4, 5, 12 power down time t pd C 12 C 15 C 20 ns 4, 5, 12 undefined output/dont care falling input rising input address d out data valid t oh t aa t rc current supply ce2 oe d out t oe t olz t ace1, t ace2 t chz1, t chz2 t clz1, t clz2 t pu t pd i cc i sb 50% 50% t ohz data valid t rc 1 ce1
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? $6 : & 497 $6 : & 497 $6 : & 497 $6 : & 497 # # # # ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 5: 5: 5: 5: 6 6 6 65 5 5 5$ $ $ $0 0 0 0 :ulwh # f\foh #+ ryhu # wkh # rshudwlqj # udqjh , 11 :ulwh # zdyhirup #4+ :( # frqwuroohg , 10, 11, 12 :ulwh # zdyhirup #5#+ &( 4 # dqg # &( 5# frqwuroohg , 10, 11, 12 parameter symbol -12 -15 -20 unit notes min max min max min max write cycle time t wc 12 C 15 C 20 C ns chip enable (ce1 ) to write end t cw1 9 C 10 C 12 C ns 12 chip enable (ce2) to write end t cw2 9 C 10 C 12 C ns 12 address setup to write end t aw 9C10C12C ns address setup time t as 0C0C0C ns12 write pulse width t wp 8C9C12C ns address hold from write end t ah 0C0C0C ns data valid to write end t dw 6C7C8C ns data hold time t dh 0C0C0C ns4, 5 write enable to output in high z t wz C5C5C5 ns4, 5 output active from write end t ow 3C3C3C ns4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t aw address ce1 we d out t cw1, t cw2 t wp t dw t dh t ah t wz t wc t as ce2 data valid d in
6 6 6 65 5 5 5$ $ $ $0 0 0 0 $6 : & 497 $6 : & 497 $6 : & 497 $6 : & 497 ? 5; 5; 5; 5; $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 'dwd # uhwhqwlrq # fkdudfwhulvwlfv #+ ryhu # wkh # rshudwlqj # udqjh , 13 'dwd # uhwhqwlrq # zdyhirup # $& # whvw # frqglwlrqv 1rwhv 1during v cc power-up, a pull-up resistor to v cc on ce1 is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, and c. 4t clz and t chz are specified with cl = 5pf as in figures b or c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed, but not 100% tested. 6we is high for read cycle. 7ce1 and oe are low and ce2 is high for read cycle. 8 address valid prior to or coincident with ce1 transition low and ce2 transition high. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce1 or we must be high or ce2 low during address transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 ce1 and ce2 have identical timing. 13 2v data retention applies to the commercial operating range only. 14 c = 30pf, except on high z and low z parameters, where c = 5pf. parameter symbol test conditions min max unit v cc for data retention v dr v cc = 2.0v ce1 3 v cc C0.2v or ce2 0.2v 2.0 C v data retention current i ccdr C60a chip enable to data retention time t cdr 0Cns operation recovery time t r t rc Cns v cc ce1 t r t cdr data retention mode v cc v cc v dr 3 2.0v v ih v ih v dr - output load: see figure b or figure c. - input pulse level: gnd to 3.0v. see figure a. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 10% 90% 10% 90% gnd +3.0v figure a: input pulse 2ns 255 w c (14) 480 w d out gnd +5v figure b: 5v output lo ad 255 w c (14) 320 w d out gnd +5v figure c: 3.3v output load 168 w thevenin equivalent: d out +1.728v (5v)
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? $6 : & 497 $6 : & 497 $6 : & 497 $6 : & 497 # # # # ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 5< 5< 5< 5< 6 6 6 65 5 5 5$ $ $ $0 0 0 0 7\slfdo # '& # dqg # $& # fkdudfwhulvwlfv # supply voltage (v) min max nominal 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb ambient temperature (c) C55 80 125 35 C10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature a vs. supply voltage v cc i cc i sb i cc i sb ambient temperature (c) -55 80 125 35 -10 0.2 1 0.04 5 25 625 normalized i sb1 (log scale) normalized supply current i sb1 vs. ambi ent te mperature a v cc = v cc (nominal) supply voltage (v) min max nominal 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature (c) C55 80 125 35 C10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 075 100 50 25 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current i cc vs. ambi ent temperature a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc v cc = v cc (nominal) t a = 25c v cc = v cc (nominal) t a = 25c output voltage (v) v cc 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) v cc output sink current (ma) output sink current i ol vs. output voltage ol vs. output voltage oh 0 20 60 80 40 100 120 140 v cc = v cc (nominal)pl t a = 25c v cc = v cc (nominal) t a = 25c capacitance (pf) 0 750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change d t aa vs. output capacitive loading v cc = v cc (nominal) 00
6 6 6 65 5 5 5$ $ $ $0 0 0 0 $6 : & 497 $6 : & 497 $6 : & 497 $6 : & 497 ? 63 63 63 63 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 ',' #440533440 $ 1#425:233 3dfndjh # glphqvlrqv 2ughulqj # frghv 3duw # qxpehulqj # v\vwhp package\ access time volt/temp 12 ns 15 ns 20 ns plastic dip\300 ml 5v commercial AS7C164-12pc AS7C164-15pc AS7C164-20pc plastic soj\300 ml 5v commercial AS7C164-12jc AS7C164-15jc AS7C164-20jc as7c 164 x Cxx x c sram prefix device number blank = standard power access time package code: p=pdip 300 mil j=soj 300 mil commercial temperature range, 0c to 70c c ea a seating b a1 e1 e d e l s plane b a pin 1 28-pin pdip min max a - 0.175 a1 0.010 - b 0.058 0.064 b 0.016 0.022 c 0.008 0.014 d - 1.400 e 0.295 0.320 e1 0.278 0.298 e 0.100 bsc ea 0.330 0.370 l 0.120 0.140 a 0 15 s - 0.055 28-pin soj min max a - 0.140 a1 0.025 - a2 0.095 0.105 b0.028 typ b0.018 typ c0.010 typ d - 0.730 e 0.245 0.285 e1 0.295 0.305 e2 0.327 0.347 e 0.050 bsc e d e1 pin 1 b b a1 a2 c e seating plane e2 a
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